1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection of circuitry. More particularly, the present invention relates to ESD protection NMOS devices with enhanced triggering property and improved ESD robustness. According to one preferred embodiment of the present invention, an improved ESD protection NMOS device possessing a trigger voltage of about 43 volts and a second breakdown current (It2) of up to 2300 mA (measured by the transmission line pulse generator) is obtained.
2. Description of the Prior Art
Electro-static discharge (ESD) is a significant problem in integrated circuit design, especially for devices with high pin counts and circuit speeds. ESD refers to the phenomena wherein a high-energy electrical discharge of current is produced at the input and/or output nodes of an integrated circuit (IC) device as a consequence of static charge build-up on the IC package. The static charge build up can result from handling of the IC device by a human body or from handling by IC device manufacturing equipments. It is known that the inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features. For example, ESD-induced spikes can rupture the thin gate oxide of a field effect transistor (FET), or simply degrade the P-N junction of a semiconductor device, effectively destroying proper IC operation. A typical “gate oxide” in a MOS transistor will rupture when its dielectric strength is more than approximately 107 V/cm.
A variety of prior art ESD protection circuits are available. These prior art circuits can be based on Zener diodes, bipolar junction transistors, and/or field effect transistors (FETs). The circuits can be connected between input/output (I/O) pins and Vcc or Vss power supply pins. There have been many approaches to lower the ESD triggering voltages. One suggestion is found in U.S. Pat. No. 5,870,268 to Lin et al., which teaches generating, in response to an ESD event, a current spike that drives up the voltage of the P-well surrounding the ESD device. The higher P-well voltage lowers the trigger voltage of the ESD NMOS device. However, this approach requires additional circuitry.
It is often desired to have ESD devices built onto IC chips that can be reliably triggered at fairly low levels. As the sizes of the semiconductor MOS devices shrink to deep sub-micron scale, it becomes more difficult to control the “snapback” effect. Accordingly, there remains an unsatisfied need for more sensitive and faster responding ESD circuits. There is also a need for a simple IC structure that provides a low ESD trigger level reliably without extensive overhead circuitry and with an efficient use of IC space.